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path: root/community/qemu/0001-linux-user-fix-build-with-musl-on-ppc64le.patch
blob: c3a918775ac0bcd10765686b4c1f81e0ac9f201c (plain) (tree)
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--- a/linux-user/host/ppc64/hostdep.h
+++ b/linux-user/host/ppc64/hostdep.h
@@ -25,7 +25,11 @@
 static inline void rewind_if_in_safe_syscall(void *puc)
 {
     ucontext_t *uc = puc;
+#if defined(__GLIBC__) || defined(__UCLIBC__)
     unsigned long *pcreg = &uc->uc_mcontext.gp_regs[PT_NIP];
+#else // Musl
+    unsigned long *pcreg = &uc->uc_mcontext.gp_regs[32];
+#endif
 
     if (*pcreg > (uintptr_t)safe_syscall_start
         && *pcreg < (uintptr_t)safe_syscall_end) {
--- a/accel/tcg/user-exec.c
+++ a/accel/tcg/user-exec.c
@@ -228,6 +228,7 @@
  */
 #ifdef linux
 /* All Registers access - only for local access */
+#if defined(__GLIBC__) || defined(__UCLIBC__)
 #define REG_sig(reg_name, context)              \
     ((context)->uc_mcontext.regs->reg_name)
 /* Gpr Registers access  */
@@ -245,15 +246,42 @@
 /* Condition register */
 #define CR_sig(context)                        REG_sig(ccr, context)

+#else // Musl
+#define REG_sig(reg_num, context)              \
+    ((context)->uc_mcontext.gp_regs[reg_num])
+/* Gpr Registers access  */
+#define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
+/* Program counter */
+#define IAR_sig(context)                       REG_sig(32, context)
+/* Machine State Register (Supervisor) */
+#define MSR_sig(context)                       REG_sig(33, context)
+/* Count register */
+#define CTR_sig(context)                       REG_sig(35, context)
+/* User's integer exception register */
+#define XER_sig(context)                       REG_sig(37, context)
+/* Link register */
+#define LR_sig(context)                        REG_sig(36, context)
+/* Condition register */
+#define CR_sig(context)                        REG_sig(38, context)
+#endif
+
+
 /* Float Registers access  */
 #define FLOAT_sig(reg_num, context)                                     \
     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 #define FPSCR_sig(context) \
     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 /* Exception Registers access */
+#if defined(__GLIBC__) || defined(__UCLIBC__)
 #define DAR_sig(context)                       REG_sig(dar, context)
 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 #define TRAP_sig(context)                      REG_sig(trap, context)
+#else // Musl
+#define DAR_sig(context)                       REG_sig(41, context)
+#define DSISR_sig(context)                     REG_sig(42, context)
+#define TRAP_sig(context)                      REG_sig(40, context)
+#endif
+
 #endif /* linux */

 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)