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authorSören Tempel <soeren+git@soeren-tempel.net>2022-04-14 21:29:29 +0200
committerSören Tempel <soeren+git@soeren-tempel.net>2022-04-14 21:29:29 +0200
commitda5ecf915cd6eaa67858aedb716a2d42d1a79d8f (patch)
treee33491ddf9cb87c93df23e9403befe87c6964478
parente40574f31ff33d51771c1926de286be3d83bb687 (diff)
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community/gcc-cross-embedded: always pass RISC-V -misa-spec to as(1)
The default the RISC-V ISA version used by GNU binutils >= 2.38 is 20191213 while gcc-cross-embedded still uses the older 2.2 version of the RISC-V ISA. These two upstream patches ensure that gcc-cross-embedded will always explicitly pass the utilized ISA version to the assembler. Fixes #13657
-rw-r--r--community/gcc-cross-embedded/0001-RISC-V-Fixing-misa-spec-PR-target-104853.patch24
-rw-r--r--community/gcc-cross-embedded/0002-RISC-V-Always-pass-misa-spec-to-assembler-PR104219.patch67
-rw-r--r--community/gcc-cross-embedded/APKBUILD8
3 files changed, 97 insertions, 2 deletions
diff --git a/community/gcc-cross-embedded/0001-RISC-V-Fixing-misa-spec-PR-target-104853.patch b/community/gcc-cross-embedded/0001-RISC-V-Fixing-misa-spec-PR-target-104853.patch
new file mode 100644
index 0000000000..35f842df4a
--- /dev/null
+++ b/community/gcc-cross-embedded/0001-RISC-V-Fixing-misa-spec-PR-target-104853.patch
@@ -0,0 +1,24 @@
+From f41871dfdbd9d0c3368c0bc32d879fd5485e7abb Mon Sep 17 00:00:00 2001
+From: Kito Cheng <kito.cheng@sifive.com>
+Date: Wed, 30 Mar 2022 16:19:00 +0800
+Subject: [PATCH] RISC-V: Fixing -misa-spec [PR/target 104853]
+
+gcc/ChangeLog:
+
+ * config.gcc (riscv*-*-*): Set right default isa spec.
+---
+ gcc/config.gcc | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index d1a66cfe6e4..d69be8853bc 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -4632,6 +4632,7 @@ case "${target}" in
+ case "${with_isa_spec}" in
+ ""|default|2.2)
+ tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_2P2"
++ with_isa_spec=2.2
+ ;;
+ 20191213 | 201912)
+ tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20191213"
diff --git a/community/gcc-cross-embedded/0002-RISC-V-Always-pass-misa-spec-to-assembler-PR104219.patch b/community/gcc-cross-embedded/0002-RISC-V-Always-pass-misa-spec-to-assembler-PR104219.patch
new file mode 100644
index 0000000000..0c6c0800df
--- /dev/null
+++ b/community/gcc-cross-embedded/0002-RISC-V-Always-pass-misa-spec-to-assembler-PR104219.patch
@@ -0,0 +1,67 @@
+From 9871d39f752bc9c114ed694662a519d04896f491 Mon Sep 17 00:00:00 2001
+From: Kito Cheng <kito.cheng@sifive.com>
+Date: Tue, 25 Jan 2022 20:44:04 +0800
+Subject: [PATCH] RISC-V: Always pass -misa-spec to assembler [PR104219]
+
+Add -misa-spec to OPTION_DEFAULT_SPECS to make sure -misa-spec will
+always pass that into assembler, that prevent GCC and binutils using
+different way to interpret the ISA string.
+
+gcc/ChangeLog:
+
+ PR target/104219
+ * config.gcc (riscv*-*-*): Normalize the with_isa_spec value.
+ (all_defaults): Add isa_spec.
+ * config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Add isa_spec.
+
+(cherry picked from commit 06e32a5ebf20c11dd31bc2677bede569fef84316)
+---
+ gcc/config.gcc | 4 +++-
+ gcc/config/riscv/riscv.h | 2 ++
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index a020e0808c9..d1a66cfe6e4 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -4635,9 +4635,11 @@ case "${target}" in
+ ;;
+ 20191213 | 201912)
+ tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20191213"
++ with_isa_spec=20191213
+ ;;
+ 20190608 | 201906)
+ tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20190608"
++ with_isa_spec=20190608
+ ;;
+ *)
+ echo "--with-isa-spec only accept 2.2, 20191213, 201912, 20190608 or 201906" 1>&2
+@@ -5436,7 +5438,7 @@ case ${target} in
+ esac
+
+ t=
+-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4"
++all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec"
+ for option in $all_defaults
+ do
+ eval "val=\$with_"`echo $option | sed s/-/_/g`
+diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
+index d17096e1dfa..2808f0051c4 100644
+--- a/gcc/config/riscv/riscv.h
++++ b/gcc/config/riscv/riscv.h
+@@ -60,6 +60,7 @@ extern const char *riscv_default_mtune (int argc, const char **argv);
+ --with-arch is ignored if -march or -mcpu is specified.
+ --with-abi is ignored if -mabi is specified.
+ --with-tune is ignored if -mtune or -mcpu is specified.
++ --with-isa-spec is ignored if -misa-spec is specified.
+
+ But using default -march/-mtune value if -mcpu don't have valid option. */
+ #define OPTION_DEFAULT_SPECS \
+@@ -70,6 +71,7 @@ extern const char *riscv_default_mtune (int argc, const char **argv);
+ " %{!mcpu=*:-march=%(VALUE)}" \
+ " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \
+ {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
++ {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
+
+ #ifdef IN_LIBGCC2
+ #undef TARGET_64BIT
diff --git a/community/gcc-cross-embedded/APKBUILD b/community/gcc-cross-embedded/APKBUILD
index 15a96a39fe..8f14921098 100644
--- a/community/gcc-cross-embedded/APKBUILD
+++ b/community/gcc-cross-embedded/APKBUILD
@@ -20,7 +20,7 @@ case "$CARCH" in
esac
pkgname=gcc-cross-embedded
pkgver=11.2.0
-pkgrel=1
+pkgrel=2
pkgdesc="The GNU Compiler Collection for embedded targets"
url="https://gcc.gnu.org/"
depends="gcc"
@@ -34,7 +34,9 @@ for target in $_targets; do
makedepends="$makedepends binutils-$target newlib-$target-stage1"
done
-source="https://mirrors.kernel.org/gnu/gcc/gcc-$pkgver/gcc-$pkgver.tar.xz"
+source="https://mirrors.kernel.org/gnu/gcc/gcc-$pkgver/gcc-$pkgver.tar.xz
+ 0001-RISC-V-Fixing-misa-spec-PR-target-104853.patch
+ 0002-RISC-V-Always-pass-misa-spec-to-assembler-PR104219.patch"
options="!check"
@@ -189,4 +191,6 @@ aarch64_none_elf() {
sha512sums="
d53a0a966230895c54f01aea38696f818817b505f1e2bfa65e508753fcd01b2aedb4a61434f41f3a2ddbbd9f41384b96153c684ded3f0fa97c82758d9de5c7cf gcc-11.2.0.tar.xz
+834c3a0e6163e91d485eceb7c3438a25e43d8be888ed3d6b96f50e5386926ba1443c5fe5f0b731ecd6dad809359952bd543cd22124deccc476ae6f6945b8f2bc 0001-RISC-V-Fixing-misa-spec-PR-target-104853.patch
+0dcf680dec1989685073c7123278c0bb335d1caae75e4a226a490f26f5a0502c511e60f5a2a269f565a172fb8f5b5d96a13f5bf507d9c354c37f7e332d7bd3ed 0002-RISC-V-Always-pass-misa-spec-to-assembler-PR104219.patch
"